![]() Your Verilog modules must be compiled and simulated. If you are not doing the extra credit you must still declare the condition code outputs above but you can leave them undefined in your module. You must declare your 8-bit adder/subtractor as follows: module AddSub8Bit (result, x, y, ccn, ccz, ccv, ccc, sub) input x, y output result output con, ccz, ccv, ccc input sub For extra credit: Set four condition code bits (ccn, ccz, ccv, ccc) to indicate whether the result is negative, zero, resulted in an overflow, resulted in a carry out, respectively. Your 8-bit design will not be expandable. Next, create an 8-bit adder/subtractor by instantiating your 4-bit adder twice along with additional logic needed to handle subtraction. Write a testbench to verify your 4-bit ripple carry adder. ![]() Then, create an expandable 4-bit ripple carry adder by instantiating and connecting multiple instances of your debugged full adder. Create a testbench to thoroughly test the full adder. ![]() Build a 1-bit full adder using a behavioral dataflow description. Create the design in a hierarchical fashion as follows. ![]() If sub is 1, perform a subtract if sub is o perform an addition. Your design should accept two twos-complement 8-bit inputs (x and y) and generate an output (result) which is either their sum or difference, based on another input (sub). Design and simulate an 8-bit adder/subtractor using a hierarchical Verilog behavioral dataflow description. ![]()
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